1. Field of the Invention
The present invention relates to a CMOS clamped sense amplifier. Sense amplifiers are used to amplify output signals from semiconductor storage arrays such as static random access memories, programmable read-only memories and programmable logic devices. Each of these storage arrays needs to be "sensed" to read the data stored in the devices. This data is stored within semiconductor structures in the array which are generally capable of producing only very low level output signals which indicate the data. These output signals are binary, ones or zeros, and the difference between the two binary levels is very small. Accordingly, a sense amplifier is required to amplify the level of these signals in order to further utilize them.
2. The Prior Art
Most prior art sense amplifiers used in complementary MOS ("CMOS") technologies employ a CMOS clamp at the input to reduce the input signal swings and thus the propagation delay of data through the sense amplifier. Reducing the delay through the sense amplifier is important in order to minimize delays in accessing data stored in the device.
The purpose of the input clamp circuit on prior art devices is to limit the swing of the input voltage to a magnitude just large enough to provide a full CMOS voltage level voltage swing (for example, from ground or V.sub.ss +0.2 volts to V.sub.cc -0.2 volts) at the output of the amplifier voltage gain stage. Unclamped circuits providing unlimited input voltage swings tend to be slower because of the additional time it takes to slew the excessive voltage swings beyond that required to properly operate the voltage gain stage. Moreover, the clamp circuit in prior art devices is designed to track with the voltage gain stage so that variations in processing, supply voltage and temperature are tolerated and still insure that the center point of the input voltage swing remains equal to the trip point of the transistors in the voltage gain stage. It has been found that limiting the magnitude of the input swing voltage using an input clamp circuit, followed by adjusting the mid-level output voltage from the clamp circuit to match the trip point of the voltage gain stage, improves the overall speed of the sense amplifier circuit.
Clamped sense amplifiers of the prior art have one disadvantage. When the input signal to the sense amplifier is rising, one of the CMOS transistors of the clamping circuit is turned on, pulling the input signal towards ground. Since the input signal is rising while at the same time is being pulled towards ground by the clamping circuit, the time required for the input signal to rise to its maximum level is increased. The reverse situation takes place when the input signal is falling, since the other MOS transistor in the input clamp is turned on and thus tends to pull the input voltage level towards the positive power supply voltage. This also fights the fall of the input signal, again causing delay.
Accordingly, although CMOS input clamp circuits limit voltage swings and generally speed up the operation of the sense amplifier, the improvement obtained from these clamping circuits is diminished to some considerable extent by this counteraction by the input clamping circuit of the rise and fall of the input signal voltage.
For example, if the input signal to a clamped sense amplifier of the prior art starts out a low voltage, for example, 0.5 volts, and begins to rise to its high voltage of approximately 2 volts, the N-channel CMOS transistor of the CMOS clamp is turned on when the input voltage reaches approximately 0.8 volts and its gate voltage increases as the input signal continues to rise. This has the effect of turning on the N-channel MOS transistor harder as the input rises, which actually opposes the input signal rising transition. Similarly, when the input signal falls from its high level to a low level, the other P-channel transistor of the input CMOS clamping transistor pair has the same effect of slowing down the input signal fall. The amount by which the input signal transitions are slowed (as a result of increased rise and fall times) is directly proportional to the amount of the reduction of the input swing magnitude obtained by the CMOS clamp. In other words, the better the clamping, the more the undesirable input signal transition delay which results. It would, therefore, be desirable to have an input clamping circuit which is capable of reducing the input voltage swing magnitude without causing a concomitant undesirable increase in input signal voltage transition time.